Most computational or process control tasks can be subdivided into a series of relatively simple steps or decisions. An engineer can analyze a task and design a logic scheme which can be implemented in a custom-designed circuit such as an ASIC or in a general purpose CPU such as an 8086 or Z-80. In a traditional implementation, a general purpose CPU can perform a wide variety of functions but must operate in a synchronous manner, processing only one step at a time. An ASIC can perform a variety of functions simultaneously and to a large extent asynchronously, but an ASIC can only implement the scheme for which it was designed. Thus an ASIC provides high speed but only for a specific functionality and a general purpose CPU provides great flexibility but at limited speed.
A central processing unit or "CPU", as used in this disclosure, is taken to mean a von Neumann machine. A minimum von Neumann machine can read input, write output which is dependent on the input, and includes both invert and add functions. These principle components and functions provide the basis for some very sophisticated devices but each is still a CPU.
A logic scheme can also be implemented in a programmable logic device (PLD) such as a field programmable gate array (FPGA). PLDs are available from several manufacturers, including Xilinx, AT&T, Altera, Atmel and others. In general, a PLD can operate much faster than a general purpose CPU and can handle asynchronous processes. A PLD is rarely as fast as an ASIC but does allow changes to the logic scheme.
The field of configurable hardware is well known and has been the subject of intense engineering development for the last few years. See in general the background section of co-pending, commonly-assigned U.S. patent application Ser. No. 07/972,933, filed Nov. 5, 1992, and now abandoned, entitled "SYSTEM FOR COMPILING ALGORITHMIC LANGUAGE SOURCE CODE INTO HARDWARE," which is incorporated in full herein by reference.
Previous implementations of PLDs, however, generally have been used only for a specific logic scheme which is changed only if the logic needs to be redesigned. Up until now, PLDs have been used to implement logical functions without using op codes since providing logical resources to interpret and execute op codes takes up precious resources.
A typical PLD application is as a monitor controller on a video board. As new monitors are released on the market or as the board designer develops an improved algorithm, the vendor may release revised configuration software for the PLD. This software can be distributed through traditional channels such as downloading from a bulletin board or asking the user to visit a distributor to have the new configuration loaded. Such revisions are relatively infrequent, possibly months or years apart.
An alternative way to implement logic functions is to load functions in hardware only as needed. This is particularly useful when certain functions are needed only rarely and only a limited amount of hardware resources are available. Thus the engineer would prefer to use the available resources for the most frequently used functions. Using techniques well known in cacheing schemes, the engineer can provide a variety of functions, each in a form ready to load as a configuration file, and load or unload functions as needed.
Until this time, engineers have only begun to consider the possibility of "cacheing" functions as hardware configurations. The present method provides a way to implement a wide variety of functions in programmable hardware devices.